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Transconductance Boosting Technique for Bandwidth Extension in Low-Voltage and Low-Noise Optical TIAs

B Abdollahi, B Mesgari, S Saeedi, E Roshanshomal, A Nabavi, ...
Journal Papers , , {Pages }

Abstract

Ultra-low-noise TIA topology for MEMS gyroscope readout

Mahziar Serri, Saeed Saeedi
Journal PapersAEU-International Journal of Electronics and Communications , 2020 February 29, {Pages 153145 }

Abstract

This paper proposes a TIA topology that can be used in accelerometer and gyroscope systems. The proposed TIA topology considerably relaxes the trade-off among the transimpedance gain, bandwidth, and input referred current noise without increasing the power consumption. Furthermore, this paper presents a model for gyroscope microelectromechanical systems (MEMS) resonator that enables us, unlike prior works, to predict the resolution of the gyroscope system at the early stage of the design. In this model, the noise arising from driving loop blocks is compared with the noise of sense channel blocks. It has been illuminated that the noise of sense transimpedance amplifier (TIA) is the most influential in the resolution of the gyroscope system.

Cell Weighting and Gate Inductive Peaking Techniques for Wideband Noise Suppression in Distributed Amplifiers

Baset Mesgari, Saeed Saeedi, Abumoslem Jannesari
Journal PapersIEEE Transactions on Circuits and Systems I: Regular Papers , 2020 July 7, {Pages }

Abstract

This paper presents a noise suppression method to improve noise figure (NF) performance of a distributed amplifier (DA) in a broad frequency range. In the proposed DA topology, the input matching resistor, which remarkably increases the NF, is replaced by a common-gate (CG) stage. The noise contribution of the CG terminating network is suppressed by employing a cell weighting plan in conjunction with a gate-inductive peaking technique. Analytical methods and a circuit implementation in a 0.18 μm CMOS technology verify that the proposed noise suppression technique provides lower NF compared with the conventional DA (CDA) topology in the entire frequency range. This is in contrast to other reported low-noise DA topologies which decrease the

Analysis of Timing Accuracy and Sensitivity in a RF Correlation-Based Impulse Radio Receiver With Phase Interpolation for Data Synchronization

Sudabeh Fotoohi Piraghaj, Saeed Saeedi
Journal PapersIEEE Transactions on Circuits and Systems I: Regular Papers , 2019 March 1, {Pages }

Abstract

This paper presents an analytical method for the performance evaluation of the correlation-based impulse radio (IR) receivers, which detect the data based on synchronizing the received signal with a locally generated template pulse. In this paper, a phase interpolation technique is employed to preserve synchronization accuracy with low power consumption. The analytical method computes the spectral density of jitter at the phase interpolator output, resulting from both flicker and thermal noise components. The analysis considers the aliasing phenomenon due to the sampling of the noise to predict the induced jitter accurately. Bit error rate (BER) of the receiver is also statistically estimated in terms of the induced jitter on the template p

Design of a Comparator-Based Silicon Oscillating Accelerometer with a Comprehensive MEMS Model

Mahziar Serri, Saeed Saeedi
Conference Papers2019 27th Iranian Conference on Electrical Engineering (ICEE) , 2019 April 30, {Pages 125-129 }

Abstract

This paper presents a novel topology for silicon oscillating accelerometer (SOA). The proposed comparator-based SOA improves the low-noise-frequency and enhances the resolution by about 57% compared with the conventional SOA. It has also the more compact topology. Furthermore, this paper presents a model for accelerometer microelectromechanical systems (MEMS) resonator that predicts performance metrics of the accelerometer system at the early stage of the design. The circuit is simulated in 0.18 μm CMOS technology with supply voltage of 1.5V. The simulated resolution of the proposed SOA is 0.4 μg/✓Hz.

Analysis and Design of a Type-III PLL-based Frequency Synthesizer for FMCW Radar Applications

Salavat Ali Alaee, SAEED SAEEDI
Journal Papers , Volume 10 , Issue 100797, 2019 January 1, {Pages 18-May }

Abstract

In this paper, a fractional-N frequency synthesizer based on type-III phase locked loop (PLL) architecture is proposed for frequency modulated continuous wave (FMCW) radar systems. Analysis of the type-III PLL shows that it generates linear frequency ramps more accurately compared with its type-II counterpart and its steady-state phase error is zero, independent of the loop bandwidth and rate of the frequency variation. Considering the stability issues, power consumption, output phase noise and accuracy of the frequency ramp generation, design procedure of the type-III FMCW frequency synthesizer is presented in this paper. Based on this procedure, a fractional-N frequency synthesizer, which generates the triangular frequency sweep by a delt

Stability analysis and compensation technique for low-voltage regulated cascode transimpedance amplifier

Behnam Abdollahi, Baset Mesgari, Saeed Saeedi, Abdolreza Nabavi
Journal PapersMicroelectronics Journal , Volume 71 , 2018 January 31, {Pages 37-46 }

Abstract

Stability of low voltage regulated cascode (RGC) transimpedance amplifier (TIA) with level shifter path is analyzed and criterions for a well-behaved time response are derived. It is shown that there is a trade-off between the amplifier bandwidth and stability in this topology. Improving bandwidth by increasing transconductance of transistors leads to ringing in the step response of the amplifier and finally its instability. To add a degree of freedom to design of the low-voltage RGC circuit for high-speed optical receivers, a compensation technique is proposed in this paper and employed in a TIA circuit, designed in a 0.18 μm CMOS technology. Post layout simulation results show a gain of 52 dBΩ and bandwidth of 3 GHz in presence of a 2 p

Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

Mahsa Abomaashzadeh, Abdolreza Nabavi, Saeed Saeedi
Journal PapersInternational Journal of Circuit Theory and Applications , Volume 46 , Issue 4, 2018 April , {Pages 855-867 }

Abstract

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMOS

Selectivity and sensitivity enhancement methods for high‐data‐rate super‐regenerative receiver

Samaneh Mousavi, Saeed Saeedi
Journal PapersInternational Journal of Circuit Theory and Applications , Volume 45 , Issue 12, 2017 December , {Pages 2085-2110 }

Abstract

This paper describes selectivity and sensitivity performance evaluations and improvement methods for an on–off keying super‐regenerative (SR) receiver. A slope‐controlled quasi‐exponential quench waveform, generated by a low‐complexity PVT‐tolerant quench generator circuit, is proposed to increase data rate and reduce the receiver 3‐dB bandwidth, thereby preventing oscillation caused by out‐of‐band injected signals and improving the receiver selectivity. The SR receiver sensitivity is also enhanced by a noise‐canceling front‐end topology with single‐ended to differential (S2D) signal converter. To exemplify these techniques, we designed an SR receiver with the proposed front‐end and quench waveform generator in a

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

Vahid Sabouhi, Esmaeil Najafi Aghdam, Saeed Saeedi
Journal PapersInternational Journal of Circuit Theory and Applications , Volume 45 , Issue 1, 2017 January , {Pages 63-82 }

Abstract

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design proce

Pipelining method for low-power and high-speed SAR ADC design

Ziba Fazel, Saeed Saeedi, Mojtaba Atarodi
Journal PapersAnalog Integrated Circuits and Signal Processing , Volume 87 , Issue 3, 2016 June 1, {Pages 353-368 }

Abstract

A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel operation sequence, without adding re

Edge-combining multi-phase DLL frequency multiplier with reduced static phase offset and linearized delay transfer curve

Mostafa Hassani, Saeed Saeedi
Journal PapersAnalog Integrated Circuits and Signal Processing , Volume 82 , Issue 3, 2015 March 1, {Pages 705-718 }

Abstract

An edge-combining delay-locked loop (ECDLL) frequency multiplier with multi phase outputs is presented. In contrast to architectures based on phase-locked loop, the proposed frequency multiplier produces outputs with 25?% duty cycle without operating at multiple times of the required output frequency. Level of reference spurs at the DLL outputs is reduced by a static phase error suppression technique. In this technique, reset pulse of phase detector (PD) is used to steer charge pump (CP) currents to a dummy branch during idle interval of PD and eliminate CP current mismatch effect. This paper also presents a delay cell with linear transfer curve to increase control range of delay line and provide rather constant loop paramete

Digital cellular implementation of Morris-Lecar neuron model

Meisam Gholami, Saeed Saeedi
Conference PapersElectrical Engineering (ICEE), 2015 23rd Iranian Conference on , 2015 May 10, {Pages 1235-1239 }

Abstract

The detailed biological neuron models such as Morris-Lecar cannot be easily implemented using conventional digital or analog Euler-based methods due to the presence of nonlinear functions and complex operations in their equations. This study presents an efficient cellular-based digital architecture for implementing Morris-Lecar neuron model. Digital hardware post synthesis results show that this hardware model is able to reproduce various responses of the biological model. The proposed architecture is not dependent on the complexity of the equations, and applies no function approximation method to deliver implementable equations. This implies that all other detailed neuron models can also be implemented by this structure. High programmabili

An enhanced-gain analog correlator for sensitivity improvement in coherent impulse radio receivers

Sudabeh Fotoohi Piraghaj, Saeed Saeedi
Conference PapersElectrical Engineering (ICEE), 2015 23rd Iranian Conference on , 2015 May 10, {Pages 1103-1108 }

Abstract

A circuit technique called template range enhancement (TRE) is proposed for analog correlators employed in ultra-wideband coherent impulse radio (IR-UWB) receivers. In these receivers, the analog correlator multiplies the received signal with a template signal to detect the incoming pulses. Compared to other IR-UWB architectures, the coherent architecture has better signal-to-noise ratio (SNR) performance. To reduce the noise effect of baseband circuits in this receiver type, gain of the front-end blocks, which consists of a low noise amplifier and the analog correlator, should be increased. The conventional analog correlators, which are designed based on Gilbert cell topology, cannot provide sufficient gain for this purpose. The proposed T

Design method for a reconfigurable CMOS LNA with input tuning and active balun

Fatemeh Akbar, Mojtaba Atarodi, Saeed Saeedi
Journal PapersAEU-International Journal of Electronics and Communications , Volume 69 , Issue 1, 2015 January 1, {Pages 424-431 }

Abstract

A method to design a tunable low noise amplifier (LNA) for multiband receivers is proposed. This paper also presents a single-ended to differential conversion (S2DC) topology which improves the LNA linearity without degrading its noise performance. Combining input tuning with S2DC in a single stage reduces power consumption of the LNA and decreases effects of supply noise. An LNA has been designed based on the proposed method for 2.3–4.8?GHz in a 0.18?μm CMOS technology. Simulations show an IIP3 of −3.2?dBm, a less than 3.7?dB noise figure (NF), a voltage gain of 24?dB in the whole frequency range. The LNA draws 13.1?mW from a 1.8?V supply. The results indicate that the proposed tuning method satisfies the input matching requirement an

A low voltage low noise transimpedance amplifier for high-data-rate optical recievers

Behnam Abdollahi, Pouria Akbari, Baset Mesgari, Saeed Saeedi
Conference PapersElectrical Engineering (ICEE), 2015 23rd Iranian Conference on , 2015 May 10, {Pages 1187-1192 }

Abstract

This paper presents a trans-impedance amplifier (TIA) circuit topology which can be employed in high-data-rate optical receivers. Compared to the conventional regulated cascode (RGC) topology, the proposed circuit requires lower supply voltage and power. Based on the proposed topology, a TIA is designed in a 180-nm CMOS technology. Post layout simulation results show that the circuit can be used in wide band optical communication systems. Consuming 2.3mW from a 1.8 V supply, the circuit has 20 GHz bandwidth and 44.5 dB gain with a 150 fF photo diode parasitic capacitor. The input referred noise of the circuit is lower than 22 pA/√Hz.

Determination of composite system adequacy equivalents using a reduction technique: A case study on a regional electric company

Reza Keypour, Hessam Golmohamadi, MS Jahan, Saeed Saeedi, Asghar Akhundi, G Reza Asaseh
Conference Papers2015 30th International Power System Conference (PSC) , 2015 November 23, {Pages 32-37 }

Abstract

Reliability evaluation of a large-scale composite power system faces to numerous events/outage and consequently imposes an extensive burden of calculations. In order to simplify the problem, determination of an equivalent system for large-scale power system is inevitable. This paper proposes a framework as reduction technique to separate a composite power system to three areas: external area, optimization area and equipment outage area. This separation enables policy makers of power systems to evaluate reliability of large-scale power systems with less time of calculation and extraordinary precision. The reduction technique is applied to composite power system of Iran with more than 4600 buses to determine an equivalent network for reliabil

A wideband low noise distributed amplifier with active termination

Baset Mesgari, Saeed Saeedi, Abumoslem Jannesari
Conference PapersTelecommunications (IST), 2014 7th International Symposium on , 2014 September 9, {Pages 170-174 }

Abstract

In this paper, a distributed amplifier (DA) with a feed forward path is presented to reduce noise effects of input matching termination at the output. The proposed active termination (AT) technique also improves the amplifier gain without increasing its power consumption. To validate the introduced method, a four-stage wideband actively terminated DA (ATDA) is designed in a 0.18 μm CMOS technology and compared with a conventional DA (CDA) with passive termination. Simulation results show that the proposed technique improves the average noise figure (NF) of the DA by 0.6 dB and increases its gain by about 2 dB in a frequency range from 100MHz to 12 GHz, without increasing the power consumption.

Noise Canceling Balun-LNA with Enhanced IIP2 and IIP3 for Digital TV Applications

Saeed Saeedi, Mojtaba Atarodi
Journal PapersIEICE transactions on electronics , Volume 95 , Issue 1, 2012 January 1, {Pages 146-154 }

Abstract

An inductorless low noise amplifier (LNA) with active balun for digital TV (DTV) applications is presented. The LNA exploits a noise cancellation technique which allows for simultaneous wide-band impedance matching and low noise design. The matching and amplifier stages in the LNA topology perform single-ended to differential signal conversion with balanced output. The second and third-order nonlinearity of the individual amplifiers as well as the distortion caused by the interaction between the stages are suppressed to achieve high IIP2 and IIP3. A method for intrinsic cancellation of the second-order interaction is employed to reduce the dependence of the IIP3 on the frequency spacing between the interfering signals in the two-tone test o

Evaluation of residues of DDT and DDA in fish collected from Caspian Sea, Iran

LAMUKI MOHAMMAD SHOKRZADEH, SARAVI SEYED SOHEIL SAEEDI, NASRIN OTADI
Journal Papers , Volume 6 , Issue 18, 2012 January 1, {Pages 704-708 }

Abstract

BackgroundPesticides are essential in modern agricultural practices but due to their biocide activity and potential risk to the consumer, the control of pesticide residues in foods is a growing source of concern for the general population. Extensive application of such agents as organochlorine pesticides in farmlands and contemporary agricultural industries has led to undesired environmental contamination and human health hazards. Thus, this study attempted to evaluate and analyze the residual values of the organochlorine insecticide DDT and its metabolite DDA in the four species of most consumed fish collected from the Caspian Sea.MethodsIn this investigation, concentrations of residual values of DDT and DDA were quantitatively determined

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